The present invention relates to a semiconductor memory device and a method for fabricating the same.
A NAND-type non-volatile semiconductor memory that can electrically rewrite data changes an amount of charge in a charge storage layer of a cell gate transistor to change a threshold voltage and records the data. Generally, electrons are discharged/injected between the charge storage layer and a semiconductor substrate via a gate insulating film to control the amount of the charge in the charge storage layer.
In a NAND-type non-volatile semiconductor memory according to a first conventional technology, along a bit line direction, a plurality of cell gates including a charge storage layer provided on a main surface of a semiconductor substrate via a gate insulating film and a control gate electrode provided on the charge storage layer via a charge block layer are aligned at a space from each other. On the main surface of the semiconductor substrate between the adjacent cell gates, a source or drain diffusion layer is provided, by which a plurality of memory cell transistors are connected in series. Further, between the adjacent cell gates, an insulating film between the cells is provided (refer to, for example, Japanese Patent Laid-Open No. 2006-310393).
For such a NAND-type non-volatile semiconductor memory, in accordance with miniaturization of a memory dimension, it is necessary to decrease impurity concentration in a source or drain diffusion layer to avoid a short channel effect (decreasing a threshold voltage of the memory cell transistor). Typically, when the memory dimension is about 50 nm, the impurity concentration in the diffusion layer is about 1×1018 to 1×1020 cm−3.
The NAND-type non-volatile semiconductor memory according to a second conventional technology, a plurality of cell gate including a charge storage layer provided via a gate insulating film on the main surface of a semiconductor layer included in a Silicon On Insulator (SOI) provided on a surface of a base via an insulating layer and a control gate electrode provided on the charge storage layer via a charge block layer are aligned at a space from each other. Between each of the cell gates, an insulating film between the cells is provided. A plurality of memory cell transistors in the NAND-type non-volatile semiconductor memory are connected by the semiconductor layer in series to perform a transistor operation of a depression type (refer to, for example, Japanese Patent Laid-Open No. 2006-294711).
For such a NAND-type non-volatile semiconductor memory, it is also necessary to decrease impurity concentration in a semiconductor layer to ensure a cut-off operation of the memory cell transistor in order to minute the memory dimension.
In both of the NAND-type non-volatile semiconductor memories described above, the impurity concentration in the diffusion layer or the semiconductor layer is set to low in order to minute the memory dimension. Therefore, when the cell transistor is turned on, resistance in the diffusion layer or the semiconductor layer caused by the decreased impurity concentration is increased to decrease a cell current, thereby causing a memory operation error.